Scaling MoS 2 Transistors to 1 nm Node

We report on the first monolayer MoS2 FETs scaled to 40 nm contacted gate pitch (CGP), corresponding to 1 nm node as defined by IRDS. The FETs deliver drive current of 0.79 $\text{mA}/\mu \mathrm{m}$ under 0.6 V drain bias with on/off ratio $> 10^{7}$ and SS = 62 mV/dec. We achieve this by developing a new Sb deposition technology which reduces $R_{\mathrm{c}}$ to below 100 $\Omega\cdot\mu \mathrm{m}$ at deep $L_{\mathrm{c}}$ scaling regime $(L_{\mathrm{c}}=20\ \text{nm})$. TCAD simulations predict that quad-stacked Mos2 nanosheet FET employing the new Sb contact reduces the gate delay by 46.6% compared to Si CMOS at 1 nm node and demonstrates superior scaling potential to the end of roadmap.