(Invited) Epitaxy Strategies for Monolithic 3D Integration of Single-Crystalline Semiconductors

Continuing miniaturization of devices has reached its limits as a means to boost the performance of cutting-edge electronic products. Instead, 3D heterogeneous integration, which involves vertically stacking wafers with embedded electronic devices, is emerging as the leading approach for augmenting performance. This method, however, demands complex procedures including: creating through-silicon vias (TSVs), filling these vias with copper, and bonding the wafers via micro-bumps or Cu hybrid bonding. Eliminating the use of wafers in this complex 3D assembly could streamline the process and reduce the length of data paths. Yet, current technologies scarcely allow for the removal and reassembly of active single-crystalline devices from wafers. Moreover, directly depositing device layers onto existing circuits presents additional hurdles. Over the last decade, we have pioneered techniques for transferring single-crystalline semiconductor device membranes, significantly advancing 3D heterogeneous integration [1-8]. More recently, we have achieved a breakthrough in monolithically growing pristine single-crystalline 2D semiconductors on non-crystalline insulators at a BEOL compatible temperature, pushing the boundaries of monolithic 3D heterointegration even further [9]. In my presentation, I will explore our unprecedented 3D integration methods and their implications for state-of-the-art electronics [9, 10], optoelectronics [11], and bioelectronics [12-13]. References: [1] Nature 544, 340 (2017), [2] Nature Materials 17, 999 (2018), [3] Nature Materials 18, 550 (2019), [4] Nature Nanotechnology 15, 272-276 (2020), [5] Nature Electronics, 2, 439 (2019), [6] Nature, 578, 75 (2020), [7] Nature Nanotechnology 15, 574 (2020), [8] Nature Nanotechnology, 17, 1054 (2022), [9] Nature, 614, 88 (2023), [10] Nature Electronics, 5, 386 (2022), [11] Nature, 614, 81 (2023), [12] Science Advances, 7, 27 (2021) [13] Science 377, 859 (2022)