Progress report on high aspect ratio patterning for memory devices

Abstract High aspect ratio (HAR) silicon nitride and silicon oxide (ONON) channel hole patterning in 3D NAND flash presents great challenges. This report summarizes some of the recent progress in patterning from the perspective of HAR etching and deposition-etch co-optimization (DECO). HAR etching mechanisms will be discussed, with a focus on how to reduce the aspect ratio-dependent etching (ARDE) effect. Highlights of the new low-temperature etch process will be presented, with significant improvement in the ARDE being observed. New simulation results from a Monte Carlo feature-scale model provide insights into ion scattering and mask interactions on the control of the channel hole profile. DECO is a new frontier to enable better control of the channel hole shape at HAR. Film tier optimization and carbon liner insertion results show improvement in channel hole profile control.