A 25.8-GHz Integer-N CPPLL Achieving 60-fs rms Jitter and Robust Lock Acquisition Based on a Time–Amplifying Phase–Frequency Detector

This article presents a 25.8-GHz integer-N charge pump phase-locked loop (CPPLL). With the proposed time–amplifying phase–frequency detector (TAPFD), the in-band noise is greatly suppressed by the phase error amplification gain of TAPFD so as to break the stringent power-noise tradeoff in the conventional CPPLL. Moreover, a frequency pull-in capability analysis is carried out to prove that the proposed phase-locked loop (PLL) features a robust lock acquisition performance. The proposed PLL is prototyped in a 65-nm CMOS process, achieving 60-fs rms jitter, 14.48-mW power consumption, and −252.8-dB FoM $_{J}$ with a 0.45-mm2 active area.