Implementation of Adaptive Filter with FPGA

An adaptive filter is realized with FPGA using top-down design idea in this paper. A FIR(finite impulse response) filter structure was used for it. Since an improved LMS (least mean square) algorithm was adopted, the operation speed of the proposed adaptive filter was twice of that of a standard LMS algorithm FIR filter. The adaptive filter was coded with VHDL, compiled and synthesized with ALTERA MaxplusII. A FLEX10K30 was selected for synthesizing, and the proposed adaptive filter occupied 70% resources of this chip. The proposed adaptive filter was simulated with MaxplusII, when the period of clock was 40ns, the filter could operate very well. The simulation results verified the correctness of the design.