德拉姆
计算机科学
可靠性(半导体)
通用存储器
延迟时间
动态随机存取存储器
嵌入式系统
可靠性工程
计算机硬件
内存管理
工程类
内存控制器
半导体存储器
功率(物理)
物理
量子力学
交错存储器
作者
Hwayong Nam,Seungmin Baek,Minbok Wi,Michael Jaemin Kim,Jaehyun Park,Chihun Song,Nam Sung Kim,Jung Ho Ahn
标识
DOI:10.1109/lca.2023.3296153
摘要
The demand for accurate information about the internal structure and characteristics of DRAM has been on the rise. Recent studies have explored the structure and characteristics of DRAM to improve processing in memory, enhance reliability, and mitigate a vulnerability known as rowhammer. However, DRAM manufacturers only disclose limited information through official documents, making it difficult to find specific information about actual DRAM devices. This paper presents reliable findings on the internal structure and characteristics of DRAM using activate-induced bitflips (AIBs), retention time test, and row-copy operation. While previous studies have attempted to understand the internal behaviors of DRAM devices, they have only shown results without identifying the causes or have analyzed DRAM modules rather than individual chips. We first uncover the size, structure, and operation of DRAM subarrays and verify our findings on the characteristics of DRAM. Then, we correct misunderstood information related to AIBs and demonstrate experimental results supporting the cause of rowhammer.
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