Process Insights into 3D-DRAM with Vertical Bit Line and Scalable GAA Transistor

A novel 3D-DRAM integration flow with vertical bit line and gate-all-around (GAA) transistor is successfully demonstrated. The process modules are thoroughly described along with the challenges and optimization. The morphological integrity and electrical functionality of GAA select transistors with monocrystalline Si channel are demonstrated. TCAD modeling predicts scaling possibilities with this architecture, corroborating its suitability for future DRAM implementation.