Multi-Vt Gate Stack Technologies for Nanosheet and CFET Devices

In this paper, we present our recent studies on multi-Vt gate stack technology elements required for Nanosheet and CFET devices, which are WFM scaling and interface dipole engineering. MoN has been proposed as a high-WF p-metal as well as a scalable barrier under nWFM. As for the interface dipole engineering, dipole-first scheme has been proposed as the alternative of dipole-last, and a Vt fine-tunable novel n-type shifter has been studied for dipole-first scheme. These material innovations are the driving force for the NS/CFET multi-Vt technology.