SnSe/MoS2 van der Waals Heterostructure Junction Field‐Effect Transistors with Nearly Ideal Subthreshold Slope

The minimization of the subthreshold swing (SS) in transistors is essential for low-voltage operation and lower power consumption, both critical for mobile devices and internet of things (IoT) devices. The conventional metal-oxide-semiconductor field-effect transistor requires sophisticated dielectric engineering to achieve nearly ideal SS (60 mV dec-1 at room temperature). However, another type of transistor, the junction field-effect transistor (JFET) is free of dielectric layer and can reach the theoretical SS limit without complicated dielectric engineering. The construction of a 2D SnSe/MoS2 van der Waals (vdW) heterostructure-based JFET with nearly ideal SS is reported. It is shown that the SnSe/MoS2 vdW heterostructure exhibits excellent p-n diode rectifying characteristics with low saturate current. Using the SnSe as the gate and MoS2 as the channel, the SnSe/MoS2 vdW heterostructure exhibit well-behavioured n-channel JFET characteristics with a small pinch-off voltage VP of -0.25 V, nearly ideal subthreshold swing SS of 60.3 mV dec-1 and high ON/OFF ratio over 106 , demonstrating excellent electronic performance especially in the subthreshold regime.