Modeling and control of L-type network impedance matching for semiconductor plasma etch

The plasma process plays a pivotal role in the semiconductor industry, facilitating the creation of transistors and memory storage cells. This fourth state of matter is achieved by energizing a gas with radio-frequency electrical power, initiating and maintaining a stable plasma during the process cycles. Given that plasma behaves as an impedance component, an impedance-matching network becomes essential for optimizing power transfer from the source to the load (plasma). While various control strategies have been proposed for different network configurations, such as L, T, and Π networks, our work focuses on the L-type network due to its simplicity and extensive application in this domain. Several significant challenges have been identified in the existing literature, including slow dynamics, a non-monotonic decline in the reflected power, and substantial deviation in the capacitors’ path. These issues collectively impact the overall performance of the matching control system. In this article, we present a new methodology to obtain a nonlinear state-space model of the matching network for its analysis and design a proportional-integral combined with feedforward control and a control Lyapunov-barrier function to assess their effectiveness in achieving convergence to the desired matching value and guiding the path of the capacitors. These approaches aim to mitigate the recurring issues caused by capacitors moving in the wrong direction, thus improving the stability and efficiency of the impedance-matching process over time.