覆盖
模具(集成电路)
还原(数学)
薄脆饼
计算机科学
晶片键合
缩放比例
材料科学
光电子学
操作系统
数学
几何学
作者
Pieter Bex,Mario González,Steven Brems,Alain Phommahaxay,Koen D’havé,Prathamesh Dhakras,Dieter H. Cuypers,Lin Ye,Eric Beyne,Jonathan Abdilla,Kawsar Ahmed Prince,Benedikt Auer,Djuro Bikaljevic,Manuel Deubler,Thiago Moura,Stefan Schmid,Pavel Seroglazov
出处
期刊:
日期:2024-09-11
卷期号:: 1-6
被引量:2
标识
DOI:10.1109/estc60143.2024.10712020
摘要
Over the past decade, significant efforts have been made to understand and reduce overlay errors in Wafer-To-Wafer (W2W) hybrid bonding processes. More recently, Die-To-Wafer (D2W) hybrid bonding is gaining a lot of attention. New generations of high accuracy D2W bonders reduce the placement accuracy errors to sub-micron levels. However, for further overlay error reduction, deeper understanding of the D2W overlay is required. Finite Element Modeling (FEM) and D2W bonding experiments using a dedicated overlay test vehicle reveal a highly linear scaling error. Next to conventional infrared (IR) overlay measurements, an indirect overlay metrology using a lithography scanner is explored, enabling detailed residual fingerprint analysis. The scaling error is caused by stress in combination with die thinning, as well as die deformation during the bonding process. To reduce the scaling error, alternative bonding nozzles and modification of the die thickness and stress are proposed and investigated.
科研通智能强力驱动
Strongly Powered by AbleSci AI