Reducing reconfiguration times of FPGA-based systems using Multi-Level Reconfiguration

Current run-time reconfigurable systems present high reconfiguration times. This is a high overhead which deeply reduce these systems' performance, and it is critical when the application has tight performance requirements. Multi-level reconfiguration (MLR) model is a good strategy to reduce the size of configuration bitstreams, reducing reconfiguration times. In this paper, a two-level reconfigurable architecture was used to quantitatively analyze these benefits of MLR. This was performed with an image operator architecture, which allows reconfiguration in two architectural levels. The results showed high reductions of reconfiguration overhead compared to current reconfiguration models and to execution times.