GDNMOS design for ESD protection in submicron CMOS VLSI

In this paper a kind of ESD protection design scheme named GDNMOS (gate driven NMOS) is investigated. GDNMOS is used more and more wildly for its excellent performance in submicron CMOS VLSI ESD protection. NMOS, inverter and the RC couple cell are the makeup in this scheme. ESD device simulation in order to evaluate the robustness of the ESD protection device is performed firstly. Device simulation in a pre_Si phase will be an economical way. NMOS parameters are optimized and its ESD performance is also appreciable in this way. By circuit level simulation the RC-time constant is ascertained to differentiate ESD and VDD power-on. The design is verified in a 0.18 ¿m salicided CMOS process finally.