外延
薄脆饼
材料科学
成核
纳米技术
光电子学
化合物半导体
半导体
可靠性(半导体)
工程物理
化学
图层(电子)
工程类
物理
功率(物理)
有机化学
量子力学
作者
Bernardette Kunert,Yves Mols,Marina Baryshniskova,Niamh Waldron,Andreas Schulze,R. Langer
标识
DOI:10.1088/1361-6641/aad655
摘要
Abstract The monolithic hetero-integration of III/V materials on Si substrates could enable a multitude of new device applications and functionalities which would benefit from both the excellent optoelectronic properties of III/V compound materials and the well-established and highly mature Si manufacturing technologies. Due to the lattice mismatch between most III/V compound semiconductors and Si substrates, monolithic growth inevitably leads to the formation of strain releasing defects which degrade the final device performance and reliability. This review paper provides an overview of current approaches and methods to control the defect formation in monolithic III/V hetero-epitaxy on (001) Si substrates. The focus is on understanding the mechanisms of defect nucleation, manipulation and confinement in order to eventually realize active III/V device layers on Si substrates with high crystalline quality. For details about device applications numerous references are listed. Although many different integration approaches are discussed in the literature, there are two main concepts for the hetero-epitaxial growth of III/V material on Si: growth on blanket Si wafers and selective area growth on patterned Si substrates. Both methods have their advantages and disadvantages with respect to defect control and could potentially enable the integration of different III/V devices on a Si platform.
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