Row Hammer Reduction Using a Buried Insulator in a Buried Channel Array Transistor

In this article, we propose an analysis of the usage of a partial isolation type buried channel array transistor (Pi-BCAT). Compared with other structures, the conventional BCAT exhibits improved characteristics in the row hammer effect (RHE) because of its shallow drain/body (D/B) junction. Nevertheless, it remains affected by the RHE and should be mitigated because it is directly related to the reliability of dynamic random access memory (DRAM) applications. The proposed device exhibits a 50% improvement in the RHE and reduces leakage current ( ${I}_{{\mathrm {OFF}}}$ ) to one-third the level of conventional BCATs while also minimizing the ON -current ( ${I}_{{\mathrm {ON}}}$ ) reduction. Moreover, to efficiently compare RHE, we compare $\Delta {V}_{\text {SN}}$ by RHE and $\Delta {V}_{\text {SN}}$ based on the gate-induced drain leakage (GIDL) according to bias conditions and the device's parameters. Finally, we optimize the parameter values of the buried insulator by considering electrical characteristics and the RHE.