Process, Bias, and Temperature Scalable CMOS Analog Computing Circuits for Machine Learning

Analog computing is attractive compared to digital computing due to its\npotential for achieving higher computational density and higher energy\nefficiency. However, unlike digital circuits, conventional analog computing\ncircuits cannot be easily mapped across different process nodes due to\ndifferences in transistor biasing regimes, temperature variations and limited\ndynamic range. In this work, we generalize the previously reported\nmargin-propagation-based analog computing framework for designing novel\n\\textit{shape-based analog computing} (S-AC) circuits that can be easily\ncross-mapped across different process nodes. Similar to digital designs S-AC\ndesigns can also be scaled for precision, speed, and power. As a\nproof-of-concept, we show several examples of S-AC circuits implementing\nmathematical functions that are commonly used in machine learning (ML)\narchitectures. Using circuit simulations we demonstrate that the circuit\ninput/output characteristics remain robust when mapped from a planar CMOS 180nm\nprocess to a FinFET 7nm process. Also, using benchmark datasets we demonstrate\nthat the classification accuracy of a S-AC based neural network remains robust\nwhen mapped across the two processes and to changes in temperature.\n