晶体管
栅氧化层
门阵列
材料科学
薄膜晶体管
光电子学
CMOS芯片
与非门
逻辑门
电气工程
计算机科学
纳米技术
现场可编程门阵列
计算机硬件
工程类
电压
图层(电子)
作者
Youngmin Jo,Jimin Kwon,Jan‐Laurens van der Steen,Auke Jisk Kronemeijer,Sungjune Jung
标识
DOI:10.1088/2058-8585/abe653
摘要
Abstract Here, we present a pseudo-CMOS NOR gate array based on dual-gate amorphous indium-gallium-zinc oxide thin-film transistors (TFTs) on plastic. We fabricated a 14 × 12 array of NOR gates which was programmed using laser-induced forward transfer printing technology to realize a negative-edge-triggered D flip-flop. Two drive transistors in a conventional NOR gate configuration were replaced by a single independently gate-controlled dual-gate transistor, which enabled us to design and fabricate a gate array with much reduced number of transistors and interconnects. We anticipate that programmable gate arrays based on dual-gate oxide TFTs can be a new route to design and fabrication of digital circuitry that will be essential for emerging applications Internet-of-Things and wearable electronics.
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