40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications

An effective standby power reduction of buffer/backup SRAM in MCU is proposed for power module IC (PMIC) less edge system in IoT applications. The proposed SRAM macro is implemented using 3.3 V thick-gate-oxide IO MOSs for effectively reducing the leakage power with source bias control techniques. Four multiples interleave wordline circuitry is also introduced to reduce read and write operating power. A test chip with 64-kbit SRAM macro is designed and fabricated using 40-nm technology. The measured data show that the leakage power is 330 nW at 65°C (47 nW at 25°C), which is 1/140 of other works. The read/write power is reduced by 60% by interleave wordline circuitry.