Gate-enclosed NMOS transistors

In order to quantitatively compare the design cost and performance of various gate styles, NMOS transistors with two-edged, annular and ring gate layouts were designed and fabricated by a commercial 0.35 μm CMOS process. By comparing the minimum W/L ratios and transistor areas, it was found that either the annular layout or its ring counterpart incurs a higher area penalty that depends on the W/L ratio of the transistor to be designed. Furthermore, by comparing the output and transfer characteristics of the transistors and analyzing the popular existing methods for extracting the effective W/L ratio, it was shown that the mid-line approximation for annular NMOS could incur an error of more than 10%. It was also demonstrated that the foundry-provided extraction tool needs significant adaptation when being applied to the enclosed-gate transistors, since it is targeted only toward the two-edged transistor. A simple approach for rough extraction of the W/L ratio for the ring-gate NMOS was presented and its effectiveness was confirmed by the experimental results with an error up to 8%.