Layered GaPS4 dielectric for two-dimensional transistors

Developing van der Waals (vdW) high-k dielectric layers is a key factor in achieving high-performance two-dimensional (2D) semiconductor field effect transistors (FETs). Here, we experimentally reveal that layered GaPS 4 flakes exhibit a high dielectric constant of up to 35 and a high capacitance density (∼2.95 μF/cm²), along with a bandgap larger than 4.15 eV. Band alignment of MoS 2 /GaPS 4 heterostructure indicates a unipolar-like barrier between MoS 2 and GaPS 4 for electrons of ∼1.92 eV. We employed GaPS 4 as gate dielectric with an equivalent oxide thickness (EOT) of 1 nm in a MoS 2 FET, and the device shows a low gate leakage current of 10 −13 A, a high on/off ratio of ∼3 × 10 8 , and minimal hysteresis (∼20 mV). Theoretical modeling confirms that weak interactions preserve the MoS 2 channel’s inherent electronic properties. Compared to other layered dielectrics, GaPS 4 in MoS 2 FETs demonstrates superior properties in terms of bandgap, dielectric constant, EOT and on/off ratio. These advantages highlight the potential of GaPS 4 for integration into 2D semiconductor FETs. • Layered GaPS₄ achieves record-high dielectric constant (k = 35) with 4.15 eV bandgap for 2D transistors. • MoS₂ transistors with GaPS₄ gate dielectric demonstrate 1 nm EOT and ultrahigh on/off ratio (∼3 ×10⁸). • Unprecedented low gate leakage (10⁻¹³ A) and minimal hysteresis (20 mV) via van der Waals interface. • Theoretical modeling confirms intrinsic MoS₂ properties preserved by weak interfacial interactions. • Band alignment reveals ∼1.92 eV electron barrier enabling potential unipolar photodetectors.