MOSFET
门驱动器
寄生元件
功率MOSFET
电感
电气工程
切换时间
电压
极限(数学)
功率半导体器件
材料科学
电子工程
工程类
晶体管
数学分析
数学
出处
期刊:2008 IEEE International Power Modulators and High-Voltage Conference
日期:2008-05-01
卷期号:: 128-130
被引量:3
标识
DOI:10.1109/ipmc.2008.4743596
摘要
The ultra-fast switching of power MOSFETs, in ~1 ns, is very challenging. This is largely due to the parasitic inductance that is intrinsic to commercial packages used for both MOSFETs and drivers. Parasitic gate and source inductance not only limit the voltage rise time on the MOSFET internal gate structure but can also cause the gate voltage to oscillate. This paper describes a hybrid approach that substantially reduces the parasitic inductance between the driver and MOSFET gate as well as between the MOSFET source and its external connection. A flip chip assembly is used to directly attach the die-form power MOSFET and driver on a PCB. The parasitic inductances are significantly reduced by eliminating bond wires and minimizing lead length. The experimental results demonstrate ultra-fast switching of the power MOSFET with excellent control of the gate-source voltage.
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