High-Density 3D Multi-Layer Via Capacitors Based on Silicon Oxide Dielectric with Ultra-Low Parasitic Parameters for Advanced ICs

High-density on-chip capacitors (MIM, DTC, ISC) provide nanosecond-level transient response for AI/GPU chips, ensuring stable operation of billions of transistors and serving as a key enabler for high-performance computing. Increasing capacitance density through three-dimensional (3D) architectures is a core direction, and establishing accurate analytical models is crucial for "first-time design success." This paper proposes and investigates a 3D multilayer via capacitor structure based on a silicon oxide dielectric layer. Through systematic simulations of multilayer high- k dielectric configurations, the influence of key physical dimensions and material parameters on capacitive performance is thoroughly analyzed. The results show that multilayer high- k stacking significantly enhances capacitance density, with particularly pronounced effects when the number of layers and materials are optimized. Based on this, an accurate analytical model is established to describe the circuit characteristics of large- scale, high- density capacitor via arrays. The model not only incorporates the inherent coaxial transmission line capacitance of the vias but also fully accounts for frequency- dependent effects, ensuring its applicability to complex array configurations. Comparison and validation with commercial simulation software show good agreement, with a maximum error of less than 5% and a substantial improvement in computational efficiency. More importantly, through structural optimization, the proposed capacitor achieves an ultra- high capacitance density exceeding 2000 nF/mm2along with low ESL and ESR, demonstrating its great potential for high- integration, high- performance 3D capacitors in advanced integrated circuits. This paper provides optimization directions for high- density 3D capacitor design, validates the reliability of the model in performance prediction, and offers methodological guidance for process- design co- optimization.