Nanosheet Width Investigation for Gate-All-Around Devices Targeting SRAM Application

Gate-all-around (GAA) transistor architecture offers more design flexibility in choosing a nanosheet width tailored for a given application. This is a unique advantage of GAA over FinFET, where the channel perimeter (Weff) is quantized, mostly determined by number of fins and fin height per device (Weff=Fin number x (2 x fin height + fin thickness)). In this paper we discuss the GAA NMOS and PMOS nanosheet width optimization to achieve the best SRAM performance. By using 3D process, device and circuit modeling, we investigate the impact of NMOS and PMOS nanosheet widths on different SRAM performance metrics. Finally, we show that implementation of different NMOS and PMOS nanosheet widths can lead to better GAA SRAM performance, significantly higher than their FinFET SRAM counterpart.