Novel Multiple-Channel Polycrystalline Silicon Thin-Film Transistors Employing Asymmetric Spacing

A novel multiple-channel structure that improves the reliability of polycrystalline silicon thin-film transistors (poly-Si TFTs) employing the sequential lateral solidification (SLS) process under high gate and drain bias stress was proposed and fabricated without any additional processes. It was successfully verified that the proposed asymmetric-spacing (AS) multiple-channel TFT effectively suppressed the threshold voltage shift by about 47% and reduced the mobility variation of the poly-Si TFT by about 3% compared with those of a conventional device by using a larger spacing in the central region of the channel area. This is possibly due to the emission of induced heat inside the device during operation. Our experimental results show that the proposed AS multiple-channel TFT has more stable electrical characteristics than the conventional-structure TFT under a high gate and drain bias condition.