Hardware Acceleration of Authenticated Encryption with Associated Data via RISC-V Instruction Set Extensions in Low Power Embedded Systems

This work compares trade-offs to implement Authenticated Encryption with Associated Data (AEAD) in resource-constrained RISC-V-based embedded systems, both with and without hardware acceleration via Instruction Set Extensions (ISEs). AES-128 in CCM mode, Ascon and ChaCha20-Poly1305 algorithms are evaluated regarding suitable metrics for embedded systems, including clock cycle count, energy efficiency, memory usage, and die area cost for ISEs that accelerate each algorithm. Total clock cycles improve AES-128 in CCM mode, Ascon and ChaCha20-Poly1305, respectively by 19.66x, 2.45x and 1.05x, while energy efficiency enhances by 17.28x, 2.84x, 1.18x. Experiments employ a Zigbee network packet evaluation scenario and incur up to 9 % area overhead. Static memory efficiency gains reach 1.56x for AES-128 in CCM mode and up to 1.41x for Ascon. Our RTL and software implementations are available at https://github.com/cggewehrIRISCV-crypto.