Evaluation of Chip-Package Interaction by Means of Stress Sensors

In this study, the chip-package interaction is analyzed by means of stress sensors with electrical simulation being initially carried out to optimize the stress sensor model. The analysis includes determination of piezoresistive coefficients along with a systematic characterization approach, starting with wafer-level measurements and finalizing with package-level measurements. Final validation is carried out using a ceramic package, where the electrical measurements fully confirm the results from mechanical simulations and thus verify the suggested proof-of-concept. Besides obtaining valuable information on the piezoresistive coefficients and validating the evaluation approach, this study also generates a guideline: in a phenomenological manner we show which mechanisms and effects need to be taken into account to provide reliable evaluation of stress distribution in a semiconductor package by using stress sensors.