Switched-Capacitor Integrator with Slew-Rate Enhancement and Low Distortion

A high accuracy, low distortion circuit technique is proposed to reduce the power consumption in switched capacitor circuits. The technique uses passive charge compensation for slew enhancement and correlated level shifting (CLS) to reduce the output swing for greatly improved linearity in switched capacitor integrators. The proposed technique is verified by implementing it in a single-bit discrete-time second-order delta sigma modulator. Simulation results show the SNDR is improved by 9 dB compared to the conventional architecture.