Signal integrity design of TSV and interposer in 3D-IC

Electrical characterization of through-silicon via (TSV) and interposer line becomes more important as 3-dimensional integrated circuit (3D-IC) is emerging. In this paper, TSV modeling is proposed and verified using 3D-EM simulation. The model has good correlation with the simulation both at insertion loss and TSV-to-TSV noise transfer function. Using the TSV model, signal integrity (SI) analysis is performed. Also, interposer line characteristics are analyzed both at frequency-and time- domain. As a result, SI can be considered based on the TSV and interposer line analyses for 3D IC design.