Techniques for Measuring Warpage of Chip Packages, PWBs, and PWB Assemblies
作者
Sung-Bum Kang,Ifeanyi Charles Ume
出处
期刊:IEEE Transactions on Components, Packaging and Manufacturing Technology [Institute of Electrical and Electronics Engineers] 日期:2013-05-21卷期号:3 (9): 1533-1544被引量:16
标识
DOI:10.1109/tcpmt.2013.2255054
摘要
One of the crucial factors for the thermo-mechanical reliability of electronic packages is warpage that occurs during the printed wiring board (PWB) fabrication, solder masking and solder reflow processes. As the quality and reliability requirements of electronic components (packages) become higher, warpage control becomes a more crucial process during the PWB fabrication (manufacturing) and package assembly processes. The warpage of PWBs, PWB assemblies and electronic packages are measured by various techniques. Each technique has both its advantages and disadvantages; therefore the choice of a particular technique depends on whether one wants to measure the warpage of a PWB, PWB assembly or chip package. This paper reviews the pros and cons, such as resolution, speed, costs, accuracy, in-line capability, flexibility, and robustness, of different techniques used for measuring the warpage of chip packages, PWBs and PWB assemblies.