A Novel 18T Hybrid Master-Slave Flip-Flop With Low Power and Delay

This paper proposes a novel design for a master-slave flip-flop that utilizes a hybrid topology and a single-phase clock, consisting of 18 transistors.Proposed Flip-Flop Circuit (PFC) is comprised of two sections,namely the master section and slave section.The main element of this design is the master section, which incorporates a level restoring circuit to retain data.The slave section employs the stacking technique to minimize leakage current. PFC primarily focuses on performance issues including delay,area and average power consumption.PFC is designed using a 45nm CMOS technology node.PFC enhances average power consumption by 26.02%, 35.84%, 32.24%, 37.50%,40.32% and 50.68% in compared to the Adaptive Data Track Flip-Flop (ADTFF), Hybrid Flip-Flop (HFF), 18-Transistor Single-Phase Clocked (18TSPC), Logic Structured Reduction Flip-Flop (LSRFF),Topologically Compressed Flip-Flop (TCFF) and Change Sensing Flip-Flop (CSFF). PFC significantly improves speed by reducing the minimum delay by 26.78%, 23.32%, 30.08%, 26.54%,29.36% and 38.79% as compared to the ADTFF, HFF, 18TSPC, LSRFF,TCFF and CSFF respectively.Monte Carlo simulations were performed to analyze the Average Power Consumption and C to Q delay parameters for 1000 samples.Lowering the PMOS transistor count minimizes the overall area design.PFC operates at clock frequency range of up to 1 GHz.