随时间变化的栅氧化层击穿
材料科学
电介质
电迁移
可靠性(半导体)
介电强度
光电子学
生产线后端
低介电常数
互连
CMOS芯片
电子工程
电容器
节点(物理)
降级(电信)
电气工程
栅极电介质
电压
复合材料
计算机科学
晶体管
工程类
量子力学
计算机网络
结构工程
物理
功率(物理)
作者
Fanfei Bai,Xinghua Song
标识
DOI:10.1109/cstic.2015.7153429
摘要
As CMOS is being scaled down to 28nm node and beyond, BEOL process must use ultra low-K film as inter-metal dielectric (IMD) layers to reduce interconnection RC delay. Compared to low-K film, ultra-low K film (K≤2.5) is more porous, softer and more hydrophilic intrinsically, and easy to be damaged by process plasma, film stress, thermal and aqueous environments. The paper focuses mainly on the BEOL processes, such as etch PET, metallization, CMP, thermal treatment impact of ultra low-k dielectrics on reliability performance of electromigration (EM) and time-dependent dielectric breakdown (TDDB) or dielectric voltage breakdown (VBD). Some optimized BEOL processes with improved control of damage on porous low k materials could lead to an acceptable EM and TDDB performance.
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