Integrated Deep Trench Capacitor in Si Interposer for CoWoS Heterogeneous Integration

To accommodate the exceedingly demanding power integrity (PI) requirements for the advanced artificial intelligence (AI) and high performance computing (HPC) components, high-K (HK) based deep trench capacitors (DTC) have been integrated the first time in the silicon interposer with through silicon via (TSV) and fine-pitch interconnects for chip-on-wafer-on-substrate (CoWoS) integration. A specific capacitance density (C s ) of up to 340 nF/mm ² is achieved over a large capacitor array, providing a total capacitance (C t ) of up to 68 μF per interposer die. The HK dielectric has intrinsic time-dependent dielectric breakdown (TDDB) lifetime of > 1,000 years at an operation voltage (V cc ) of 1.35V, and a normalized leakage current (I LK ) density < 1 fA/μm ² under 1.35V at 105° C. No discernable process-induced damage or performance degradation (capacitance, I LK & V bd tailing) were observed. The high capacitance, low leakage, large area and reliability-proven Si-interposer integrated DTC, or iCap, provides superior PI performance and therefore greatly enhances the merit of using CoWoS for the next-generation heterogeneous wafer level system integration (WLSI).