Graph-Model-Based Generative Layout Optimization for Heterogeneous SiC Multichip Power Modules With Reduced and Balanced Parasitic Inductance

Multichip silicon carbide power modules with integrated snubbers are promising for large-capacity converters with high speed and cost efficiency. In the design stage, the parasitic inductance of module layout generally attracts the primary efforts of designers because of its severe impact on dynamic performance, e.g., voltage overshoot and transient current imbalance. However, due to the complexity of the heterogeneous layout, the solution space and development efficiency are always limited by the traditional manual design approach. Thus, this article proposes a generative method to optimize the layout autonomously. First, a graph model is built to describe heterogeneous layouts with all interconnectivity and design constraints retained. Based on the model, integer programming is introduced to generate layout templates with variable geometric topologies. Then, coupled with a self-developed discrete extractor, the Pareto-front is obtained by genetic algorithm, providing a tradeoff boundary for loop inductance and branch mismatch. The proposed method is systematic, flexible, and requires few designers’ expertise. A 1200 V/240 A half-bridge module is designed and fabricated to validate its capability. The experimental results show that the loop inductance of 5.59 nH is achieved, and less than 5% of the transient current imbalance is realized under 6.2 A/ns turn-onin the rated.