Hybrid-Precision Synapse Based-on FDSOI FeFETs With Back-Gate Bias Modulation

In this work, we have characterized the impact of applying a back gate (BG) voltage ( $\textit{V}_{\text{BG}}$ ) on memory properties under the top gate (TG) read mode and the corresponding synaptic performance of fully depleted silicon-on-insulator (FDSOI) ferroelectric field-effect transistor (FeFET). By controlling the carriers at the bottom channel, the BG can play a role in amplification/reduction of conductance, tuning the dynamic range ( $\bm{>}$ 150 $\bm{\times}$ ) of postsynaptic current without significantly deteriorating the nonlinearity. Based on the modulation of dynamic range, the hybrid-precision synapse cell with multiple FDSOI FeFETs has been proposed, which is promising to be a solution for ultrahigh precision synaptic applications.