An 8.5-14GHz Fractional-N Dual-Path SPD/PFD PLL with A Complementary DTC Pair in 7nm FinFET

This paper presents a fractional-N dual-path SPD/PFD PLL (DP-SPFDPLL) featuring a complementary digital-time converter (DTC) pair. Two DTCs are introduced before the two inputs of the phase detector, controlled by complementary differential control words for DTC range reduction and INL cancellation. The required DTC range is further halved by using differential VCO outputs to retime the frequency divider output. The overall design thus collectively achieves a 4 x reduction in DTC range. Fabricated in 7nm FinFET, the DP-SPFDPLL achieves 118 fsrms jitter and −247.5-dB FoM.