Switching speed-control of an optimized capacitor-clamped normally-on Silicon Carbide JFET cascode

This paper presents the results of controlling the switching speed (dv/dt) of an optimized version of the capacitor-clamped normally-on Silicon Carbide (SiC) JFET cascode. The cascode circuit is an easy way to employ the normally-on SiC JFET in a normally-off configuration using a low-voltage Silicon (Si) MOSFET in series connection. The traditional cascode circuit exhibits some disadvantages, namely limited control of the switching speed and high frequency oscillations on the drain-source-voltage of the low-voltage Si MOSFET. The optimized capacitor-clamped cascode reduces the oscillations and enables control of the voltage and current slopes as well as implements a protection of the JFET gate. The theoretical background of the capacitor-clamped cascode and the control of voltage slope are explained and investigated experimentally.