无杂散动态范围
动态范围
总谐波失真
逐次逼近ADC
电子工程
线性
功勋
dBc公司
噪音(视频)
CMOS芯片
积分非线性
电压
工程类
电气工程
计算机科学
比较器
转换器
人工智能
图像(数学)
计算机视觉
作者
Yuekang Guo,Jing Jin,Xiaoming Liu,Jianjun Zhou
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2023-02-01
卷期号:58 (2): 474-485
被引量:1
标识
DOI:10.1109/jssc.2022.3185501
摘要
This article presents a 60-MS/s 5-MHz BW noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) with an integrated highly linear input buffer in a 40-nm CMOS process. A dynamic level-shifting (DLS) technique is proposed to adaptively adjust the output common-mode voltage of the integrated input buffer for different operation phases, achieving the optimal linearity while alleviating the voltage breakdown problem at the capacitive digital-to-analog converter (CDAC) top plate. The mismatch-error-shaping (MES) technique is utilized to minimize the CDAC mismatch, which also generates undesired inter-symbol-interference (ISI) errors as a side effect. An ISI-error correction (IEC) technique is proposed to mitigate this problem and further improve the linearity. Both foreground and background calibrations are adopted in the subranging ADC and the NS filter to improve the gain accuracy. This SAR ADC prototype, with an integrated input buffer driving a 4.4-pF CDAC within 2.7 ns, achieves signal-to-noise ratio (SNR)/signal-to-noise-and-distortion ratio (SNDR)/spurious-free dynamic range (SFDR)/dynamic range (DR)/total harmonic distortion (THD) of 85.4 dB/84.2 dB/97.3 dBc/86.4 dB/−92.9 dBc while consuming 8.06 mW from 2.5- and 1.1-V dual supply voltages. The Walden FoM (FoM $_{\mathrm {W}}$ ) and figure-of-merit (FoM $_{\mathrm {S}}$ ) are 60.6 fJ/conv.-step and 172.1 dB, respectively.
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