Load-Impedance-Insensitive Design of High-Efficiency Class EF Inverters

This letter develops a high-efficiency Class EF inverter under ultrawide load impedance variation. The inequality constraints are introduced to fully release the design potential when the partial zero voltage switching operation serves as the primary goal. The load-reactance insensitivity is discussed based on the inverter's robustness under circuit parameter variation. The switch voltage stress is also considered for the final tradeoff design. In the experiment, when the load resistance varies in [15, 40] $\Omega$ and load reactance varies [--17, 17] $\Omega$ , a 1-MHz inverter is built and shown to operate normally with efficiency above 92%.