Physical Insights Into the Impact of p-GaN Sidewall Passivation on Gate Leakage, Threshold Voltage Instability, and Gate Breakdown Behavior in p-GaN Gate AlGaN/GaN HEMTs

This work presents the impact of p-GaN sidewall passivation on gate leakage mechanisms, breakdown behavior, and threshold voltage (V_th) instability in p-GaN gate AlGaN/GaN HEMTs. At negative and low positive gate biases, thermionic conduction dominates, while gate biases above threshold trigger self-limiting electron-hole recombination in the AlGaN barrier, with electron supply from the channel and hole tunneling from the gate through the extended p-GaN region near sidewalls. At higher positive gate biases, leakage is driven by hole injection across the metal/p-GaN barrier. Improved sidewall passivation, with reduced interface acceptor trap concentration, suppresses leakage by over two orders of magnitude by limiting hole tunneling into the extended p-GaN region. Sidewall leakage also determines whether gate breakdown occurs in a single or dual stage, with improved passivation increasing breakdown voltage by 1.5V. Gate leakage analysis further indicates that a positive V_th shiftt at low positive biases results from electron trapping into the AlGaN barrier, while a negative shift at higher biases is due to hole accumulation at the p-GaN/AlGaN interface. However, under prolonged stress conditions, hole accumulation causes energy band lowering across the AlGaN barrier, thereby causing electron/hole spillover across the AlGaN barrier, which contributes to the negative V_th shift turnover. Temperature-dependent analysis shows hole emission from Mg-out diffused acceptor traps in AlGaN contributes to the positive V_th shift under negative gate bias. Extended p-GaN leakage provides a recovery path, reducing the positive shift through hole capture and enabling recombination during negative and low positive stress conditions. V_th recovery is slow under negative and low positive stress but accelerates with higher positive recovery biases, validating the proposed mechanisms and suggesting that applying such preset voltages in gate drivers can enhance stability and mitigate anomalous V_th behavior.