Implementation of a Two-Processor CPU for a Programmable Logic Controller Designed on FPGA Chip

The study presents details related to the structure of a two-processor CPU designed for a PLC. The CPU is made up of a 1-bit processor combined with a 32-bit processor and is capable of executing a control routine developed in the IL language according to requirements of the IEC 61131-3 standard. In addition, the CPU is provided with functionalities necessary to handle such functional modules as edge detectors, flip-flops, timers and counters. A dedicated module of interface memory for data exchange was developed to enable synchronization of data transfer between the two processors that are operated in absolute independent and asynchronous way. The entire CPU was implemented in resources of a programmable (FPGA) chip from the Artix-7 family offered by Xilinx. The last part of the study comprises results obtained for execution times for example control routines and these times are compared against respective results achieved for other CPU structures.