Spatially Separated Dual Floating-Gate Synaptic Memory Based on Multilayer SnS2 for Neuromorphic Computing

Two-dimensional van der Waals heterostructures are promising platforms for next-generation non-volatile memory and neuromorphic computing. This work reports a spatially separated dual floating-gate synaptic transistor based on multilayer SnS2/h-BN/1T′-WTe2-MoTe2 van der Waals heterostructures. The two floating-gate regions are independently characterized, revealing superior charge-storage capability of the 1T′-WTe2 floating gate compared with 1T′-MoTe2. The optimized device exhibits a memory window of approximately 51 V, stable program/erase operation, endurance exceeding 10^4 cycles, and retention of approximately 10^5 s. Gradual analog conductance modulation enables long-term potentiation and long-term depression and provides reliable synaptic weight updates. Experimentally measured conductance states are incorporated into convolutional neural network simulations using the Fashion-MNIST dataset, achieving approximately 92.5% classification accuracy. These results demonstrate the potential of spatially separated dual floating-gate architectures for energy-efficient neuromorphic hardware and in-memory computing applications.