Bitline etch process development for Advanced process DRAM manufacturing

DRAM continues to play a major role in the semiconductor industry. As the design rule scaled down, one of the key technologies is to obtain the sufficient sensing margin for high performance by decreasing the leakage current from bitline (BL) to storage node contact (SNC). In the bitline manufacturing, we overcome ACL hard mask collapse, SiN hard mask taper and W metal bowing issues to create 10nm~14nm CD capability of bitline for the advanced process node.