Cathode Buffer Layer for Energy‐Level Matching and Interface Passivation

Perovskite solar cells (PSCs) have demonstrated high‐power conversion efficiency (PCE) and exhibit great application potential in photovoltaic systems. Generally, a typical PSC is accompanied with multiinterfaces; therefore, charge extraction and transport in PSCs are strongly affected by these interfaces. In fact, interfacial energy‐level mismatch of carrier transport layer and anode/cathode is also deeply limiting the electrical performance of PSCs. Herein, a low‐temperature‐processed indium tin oxide (ITO‐LT) cathode buffer layer is developed and used for optimizing the energy‐level alignment and suppressing defects at the electron transfer layer and cathode interface. It is revealed that a 3 nm ITO‐LT cathode buffer layer with an appropriate energy alignment and effective defect suppression could enhance interfacial charge transfer, resulting in a PCE of 21.13% in a planar PSC.