A CMOS Image Sensor Low-Power Counter for Single-Slope ADC at 500MHz Clock Frequency and 28pJ/Conversion-Step Figure-of-Merit

This paper presents a counter-latch architecture for CMOS Image Sensors (CIS). The interface between the counter and the latches uses a low-voltage bus to reduce power consumption. The digital voltage supply is 1.2V and the lowvoltage bus uses a programmable voltage supply between 1.2 to 100mV. The power consumption, at 100MHz count frequency, is reduced from 4.21 mW at 1.2V supply to $29.8\mu ~\mathrm{W}$ at 100mV supply. The power consumption, at $500 M H z$ count frequency, is reduced from 17.58 mW at 1.2V supply to $146.2 \mu ~\mathrm{W}$ at 100mV supply. The counter has been verified with post-layout simulation in a 65 nm CMOS process.