Performance Limit of Gate-All-Around Si Nanowire Field-Effect Transistors: An Ab Initio Quantum Transport Simulation

The gate-all-around (GAA) $\mathrm{Si}$ nanowire (NW) field-effect transistor (FET) is considered one of the most promising successors of the current mainstream $\mathrm{Si}$ fin FET (FinFET) owing to its better electrostatic gate control. Experimentally, the diameter of $\mathrm{Si}$ NWs has been scaled down to 1 nm. In this paper, the performance limit of the GAA $\mathrm{Si}$ NWFET with a 1-nm diameter is investigated by utilizing ab initio quantum transport simulations. We prove that the electrical conduction is concentrated in the core of the ultranarrow wire channel. The minimum gate length (${L}_{g}$) at which the n- and p-type GAA $\mathrm{Si}$ NWFET can satisfy the high-performance application requirements (on-state current, gate capacitance, delay time, and power dissipation) of the International Technology Roadmap for Semiconductors is 3 nm. The best-performing 5-nm-${L}_{g}$ n-type GAA $\mathrm{Si}$ NWFET exhibits an energy-delay product comparable with typical monolayer two-dimensional FETs. Compared with the similar-sized trigate $\mathrm{Si}$ NW FinFET, an approximately 200% increase in the on-state current and about 15% decrease in the subthreshold swing are witnessed in GAA $\mathrm{Si}$ NWFET at the same 5-nm ${L}_{g}$. Through strain engineering, about an 80% increase of on-state current is observed in the 5-nm-${L}_{g}$ p-type GAA $\mathrm{Si}$ NWFET. Our research demonstrates the vast potential of the GAA $\mathrm{Si}$ NWFET in the sub-3-nm gate-length region.