A Modular and Scalable FPGA Platform for Intelligent, High‐Throughput Image‐Activated Cell Sorting

Image-activated cell sorting (IACS) enables high-throughput cell classification by linking cellular morphology to physiology. While integrating advanced artificial intelligence (AI) can enhance the capture of subtle morphological heterogeneity, AI models inevitably introduce greater computational complexity when addressing complex problems, leading to increased analysis latency and latency instability. High latency implies longer chip lengths, while latency instability leads to incorrect sorting timing. To address this challenge, IACS can utilize field-programmable gate array (FPGA) as a stable, low-latency image analysis tool. Here, we developed a two-stage FPGA processing system for cellular data acquisition and real-time AI inference, utilizing the high-level synthesis (HLS) framework. By deploying a customized U-Net model on the AMD-Xilinx accelerator card and integrating hardware acceleration modules including activation function approximation and pixel-level convolution acceleration, we achieved a stable segmentation latency of 3.06 milliseconds (ms) at a 272 MHz clock frequency and delivered a processing throughput of up to 16,601 frames per second (fps). Using the morphological parameters obtained after segmentation, we successfully separated deformed HeLa cells from normal cells and distinguished colorectal cells, red blood cells, HeLa cells, and microspheres. This work provides IACS with a stable and low-latency image processing solution.