21.1 A 121.7dB DR and -109.0dB THD+N Filterless Digital-Input Class-D Amplifier with an HV Multibit IDAC Using Tri-level Output and Employing a Transition-Rate-Balanced Bidirectional RTDEM Scheme

Digital-input Class-D amplifiers (CDAs) are widely used in audio applications and offer high power efficiency and high levels of integration. As human ears have a dynamic range (DR) of $\sim130$ dB, high DR is preferred in high-performance audio CDAs, and low THD+N is required for sound fidelity. Prior digital-input CDAs often employ multi-bit resistive DACs (RDACs) [1] or current-steering DACs (IDACs) [2], but their DR and THD+N are limited to $\sim115$ dB and $\sim -98$dB respectively. In [3], a capacitive-DAC-based digital-input CDA achieves high DR (120.9dB) and low THD $+\mathrm{N}(-111.2$dB). However, it is only suitable for CDAs employing an LC filter and, therefore, does not support the low-cost filterless configuration. IDACs using tri-level unit cells can potentially offer higher DR than their 2-level IDAC and RDAC counterparts, but they exhibit inferior linearity that can result in high THD+N, e.g., only -93dB THD+N in [4]. This paper presents a 14.4V filterless digital-input CDA that achieves high DR and low THD+N by employing a high-voltage (HV) multi-bit IDAC with tri-level unit cells. To overcome nonlinearity due to mismatch and ISI, a transition-rate-balanced bidirectional real-time (RT) DEM scheme is introduced. Implemented in a $0.18 \mu m$ BCD process, the prototype achieves 121.7dB DR, -104.0dB, and -109.0dB peak THD+N for 1kHz and 6kHz signals, respectively. Furthermore, it can deliver 12.7W at 10% THD into an $8 \Omega$ load with 90% efficiency.