CMOS Image Sensor With Two-Step Single-Slope ADC Using Differential Ramp Generator

This study presents a CMOS image sensor (CIS) with a two-step single-slope (TS-SS) analog-to-digital convertor (ADC), wherein the differential topology characteristics of a ramp generator are used. The proposed TS-SS ADC effectively resolves 1 most significant bit (MSB) with a half-ramping of a full analog-to-digital (A/D) reference at coarse conversion and the remaining least significant bits (LSBs) with differential slope ramping signals from the ramp generator. The proposed readout scheme maintains the existing column readout structure and does not require to regenerate the coarse-step region in each column. Moreover, the proposed TS-SS readout scheme is verified for a frame rate enhancement, that is, the efficiency increases as the bit depth of the ADC increases. A prototype CIS with the proposed 10-bit TS-SS ADC was implemented in a 1P4M 0.11- $\mu \text{m}$ CIS process with a 2.9- $\mu \text{m}$ pitch. The measurement results of the prototype CIS demonstrated the figure of merits (FoMs) of $102~\mu \text{V}\cdot $ pJ/steps and $2.79~\mu \text{V}$ /MHz/steps.