铜互连
电迁移
可靠性(半导体)
材料科学
缩放比例
互连
工程物理
铜
低介电常数
电介质
电子工程
过程集成
光电子学
可靠性工程
计算机科学
冶金
工程类
复合材料
物理
工艺工程
电信
功率(物理)
数学
热力学
几何学
出处
期刊:Electronics
[MDPI AG]
日期:2022-09-14
卷期号:11 (18): 2914-2914
被引量:31
标识
DOI:10.3390/electronics11182914
摘要
The Cu/low-k damascene process was introduced to alleviate the increase in the RC delay of Al/SiO2 interconnects, but now that the technology generation has reached 1× nm or lower, a number of limitations have become apparent. Due to the integration limit of low-k materials, the increase in the RC delay due to scaling can only be suppressed through metallization. As a result, various metallization methods have been proposed, including traditional barrier/liner thickness scaling, and new materials and integration schemes have been developed. This paper introduces these methods and summarizes the recent trends in metallization. It also includes a brief introduction to the Cu damascene process, an explanation of why the low-k approach faces limitations, and a discussion of the measures of reliability (electromigration and time-dependent dielectric breakdown) that are essential for all validation schemes.
科研通智能强力驱动
Strongly Powered by AbleSci AI