Thin Die Flip Chip Process Enablement for Stacked IC Memory Packages

In this paper, the process challenges such as thin-die flip chip (FC) attaching, underfill dispensing and Cu pillar bump stress mitigation in the IC memory stacking using non-TSV dies were investigated. For the purpose to enable the 90-um thin die attaching in mass reflow, the BEOL (Back End of Line) film stress was fine tuned to reduce die warpage at jointing temperature. Next, the voiding risk of CUF (Capillary Underfill) dispensed on the BOT (Bump-on-Trace) substrate was resolved by solder resist (SR) pattern optimization. The CPI (Chip Package Interaction) behavior of Cu pillar bump was evaluated by progressive pillar shear test. Furthermore, Cu pillar low-k stress with different bump patterns were carried out by finite element simulation, and the results show a significant stress reduction by adding dummy bump to surround active bumps at die center-spine area.